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Silicon Labs /MGM240PA32VNN /MSC_S /READCTRL

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Interpret as READCTRL

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https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/MSC_NS/READCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WS0)MODE

MODE=WS0

Description

No Description

Fields

MODE

Read Mode

0 (WS0): Zero wait-states inserted in fetch or read transfers

1 (WS1): One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details

2 (WS2): Two wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details

3 (WS3): Three wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data